Display
The PTC-701 uses a Hitachi HD44780A00 LCD controller driving a 2×16 character display (module "128-KN"). The controller is located on the daughter card and communicates with the CPU via memory-mapped registers in the AMI 9217MLB gate array.
Hardware
| Controller | HD44780A00 (Hitachi, QFP package) |
| Display | 2×16 character LCD |
| Character size | 5×8 pixels |
| LCD bias | RC4192N (negative voltage generator for contrast) |
| Font ROM | hd44780u_a00.bin (4096 bytes, 256 chars × 16 bytes/char) |
I/O Registers
0x3F50 |
W | HD44780 data register (RS=1) - character data writes |
0x3F60 |
W | Display timing/control register 1 (init: 0x10) |
0x3F62 |
W | Display timing/control register 2 (init: 0x02) |
0x3F63 |
W | Display timing/control register 3 (init: 0x02) |
0x3F80 |
W | HD44780 command register (RS=0) |
0x3FA0 |
R | Status register - bit 0 = busy flag (polled before writes) |
Initialisation Sequence
The firmware initialises the HD44780 at boot with the following commands written to 0x3F80:
0x30 |
Function Set: 8-bit (reset sequence, sent twice) |
0x38 |
Function Set: 8-bit, 2-line, 5×8 font |
0x01 |
Clear Display |
0x08 |
Display OFF |
0x06 |
Entry Mode: increment, no shift |
0x80 |
Set DDRAM address 0x00 (line 1, position 0) |
0x0C |
Display ON, cursor off, blink off |
Display Refresh
The LCD bytecode opcode (0x44, handler at 0x1848) performs a full 2×32 display refresh from the RAM buffer at 0x6080-0x60BF:
- Write 0x80 to command register (set DDRAM line 1, position 0)
- Output 32 bytes to data register from buffer (0x6080-0x608F + 0x60A0-0x60AF)
- Write 0xC0 to command register (set DDRAM line 2, position 0)
- Output 32 bytes to data register from buffer (0x6090-0x609F + 0x60B0-0x60BF)
Each character is translated through a lookup table at RAM 0x68xx before being written. A 9-cycle busy-wait is inserted between each character write.
Display Buffer Format
The buffer layout is interleaved - line 1 left half, line 2 left half, line 1 right half, line 2 right half in 16-byte chunks. For each 32-byte write per line:
- Bytes 0-15: Character data (ASCII, 0x20 = space). These are the visible characters on the LCD.
- Bytes 16-17: Separator (always 0x00)
- Bytes 18-25: Attribute flags (0x01 = cursor/underline at position)
- Bytes 26-31: Control/status bytes
Only the first 16 bytes per line produce visible characters on the physical 2×16 LCD. The attribute bytes likely control cursor appearance on the real hardware.
Font ROM
The font ROM (hd44780u_a00.bin) contains 256 characters at 16 bytes per character (5 pixels wide in bits 4-0, 8 rows used + 8 padding). The character map:
- 0x00-0x1F: CGRAM (blank in ROM, user-defined at runtime)
- 0x20-0x7F: Standard ASCII (yen sign at 0x5C, arrows at 0x7E-0x7F)
- 0x80-0x9F: Blank/unused
- 0xA0-0xDF: Japanese half-width katakana + punctuation
- 0xE0-0xFF: Greek letters, math symbols
The PTC-701 firmware only uses the ASCII range (0x20-0x7E).
Display Pipeline (R1.7)
The firmware implements a 5-stage display pipeline (SYS 3822) to build the LCD content from banked ROM data:
- Stage 1 (SYS 37BC): Load primary display text from banked ROM to buffer
- Stage 2 (SYS 379A): Load secondary/overlay data to temporary buffer
- Stage 3 (SYS 300E): Format characters (hex conversion, field extraction)
- Stage 4 (SYS 37DE): Insert formatted text at cursor positions in buffer
- Stage 5: Strip bit 7 markers from characters, then LCD refresh
Cursor positions are marked in the buffer by setting bit 7 on placeholder characters (0x5F with bit 7 = 0xDF). Stage 4 replaces these with actual data characters. Stage 5 clears bit 7 before the final write to the HD44780.