PCB
The MSI/88e is built from a main CPU board (PWB 27882-00-00), a separate LED display board (ASSY 27807) carrying two MAN2815 alphanumeric modules, and one of two RAM board variants: a 10K/12K board (PWB 27319-00-00) or a 24K board (PWB 27274). The chip inventory below was identified from photographs of the unit (msi88a_*.jpg) and the scm23c65.pdf service schematic, and cross-referenced against the firmware disassembly.
CPU board (PWB 27882-00-00)
| Qty | Chip | Function | Likely usage |
| 1 | RCA CDP1802 | 8-bit CMOS microprocessor | Main CPU (~2 MHz), running the bytecode interpreter; all I/O is polled, no interrupts. |
| 1 | SSS SCM23C65 / HP CM6400-3 | 8 KB static CMOS ROM (2764-compatible) | System firmware MSI88_2.BIN (reset vector 0x0000, init 0x1F60). |
| 2 | National MM80C98N | 16-pin tri-state hex buffer/inverter (CMOS) | Bus buffering between the CPU and the display/RAM boards. Not a UART (National/Fairchild datasheet); the MSI/88e has no UART chip on any board. |
| 1 | MM74C374N | Octal D-type latch, tri-state output | Output/display data latch. |
| 1 | Motorola MC14174B | Quad D-type flip-flop with reset | Control/status latch (recorder motor, handshake lines). |
| 2 | CD4093BE | Quad 2-input NAND Schmitt trigger | Debouncing, reset conditioning, oscillator, and FSK tone shaping for the Q-bit transmitter. |
| 1 | CD4024BE | 7-stage ripple-carry binary counter | Frequency divider for timing generation (display refresh, FSK tones). |
| 1 | CD4013BE | Dual D-type flip-flop | Debounce, divide-by-2, power-down latch. |
| 1 | MM74C08N | Quad 2-input AND gate | Address/chip-select decode logic. |
| 1 | CD4049UBE | Hex inverting buffer | Bus/line driver to the display and RAM boards. |
LED display board (ASSY 27807)
| Qty | Chip | Function | Likely usage |
| 2 | Litronix/Monsanto MAN2815 | 8-char × 14-segment alphanumeric LED module | 16-character display (segment low byte on OUT 1, segment high byte on OUT 4, digit select on OUT 2). |
| 1 | TI SN75492N | Hex high-current peripheral driver | Digit/position drive for the display modules. |
| 2 | National DS8867N | LED segment driver | Segment drivers for the MAN2815 modules. |
| 2 | MM74C164N | 8-bit serial-in/parallel-out shift register | Serialize segment data from the CPU to the segment lines. |
| 2 | MM74C374N | Octal D-type latch, tri-state output | Segment/character latches for display refresh. |
| 1 | HEF40098BP | Hex 2-input NOR buffer | Digit-select decoding/buffering (OUT 2 codes 0x43 / 0x42). |
| 1 | Intersil ICL8211CPA | Programmable voltage detector | Low-battery monitor driving the LOW BATTERY/REPLACE CELLS warning and INP 1 bit 3. |
| 1 | MM74C08N | Quad 2-input AND gate | Display decode gating. |
| 1 | CD4011BE | Quad 2-input NAND gate | Refresh/digit-decode logic. |
| 1 | CD4001BE | Quad 2-input NOR gate | Display blanking/anti-ghost logic. |
| 1 | CD4066BCN | Quad bilateral analog switch | Audio routing (key-click tone, acoustic coupler signals). |
RAM board 10K/12K (PWB 27319-00-00)
| Qty | Chip | Function | Likely usage |
| 5 | Toshiba TC5517AP-8 | 2K×8 static CMOS SRAM | 10 KB battery-backed RAM (one empty socket for the 12 KB option). Stack @ 0x809C, buffers @ 0x8100 / 0x8206. |
| 2 | CD4050BE | Hex non-inverting buffer | Address/data bus buffering between the CPU and RAM boards. |
| 1 | MM74C374N | Octal D-type latch, tri-state output | Address / data latch. |
| 1 | MM74C42N | BCD-to-decimal (1-of-10) decoder | RAM chip-select decode. |
| 1 | CD4049UBE | Hex inverting buffer | Bus buffering. |
| 1 | CD4011BE | Quad 2-input NAND gate | Decode logic. |
| 1 | CD4066BCN | Quad bilateral analog switch | Battery-backup switching (lithium “keepers” cells). |
| ? | CD40106BCN | Hex Schmitt inverter | Possibly present (debounce/oscillator). |
RAM board 24K (PWB 27274)
| Qty | Chip | Function | Likely usage |
| 12 | Fujitsu MB8416A-15L | 2K×8 static CMOS SRAM | 24 KB battery-backed RAM (upgraded memory option). |
| 2 | MM74C154N | 4-to-16 line decoder / demultiplexer | RAM chip-select decode (16 select lines cover the 12 SRAMs). |
| 1 | MM74C00N | Quad 2-input NAND gate | Select / decode logic. |
| 1 | CD4011BE | Quad 2-input NAND gate | Decode logic. |
| 1 | CD4049UBE | Hex inverting buffer | Bus buffering. |
| 1 | CD4066BCN | Quad bilateral analog switch | Battery-backup switching. |
| 1 | CD4019BE | Quad AND-OR select gate (4-bit data selector) | Bank/bus multiplexing for the SRAMs. |
Other components
-
Piezo beeper - key-click and
LOW BATTERY/REPLACE CELLSaudible warnings. - Lithium “keepers” cells - backup for the battery-backed RAM boards.
- Slide switches - OPER/PRGM mode select (read on INP 2) and POWER OFF/ON.
-
27-key membrane keyboard (
ASSY 27409) - rows strobed on OUT 2 (multiplexed with the display refresh), columns read on INP 1 bits 0-2 and 6.
How this maps to the emulation
- The MM80C98N parts are tri-state hex buffers, not UARTs - there is no UART on any board. The SEND pseudo-code opcode (0x05AC) streams the 0x810B status/display buffer over a parallel handshake interface on ports 6/7 (INP 6 busy poll, OUT 6 control byte, OUT 7 data, confirmed by trace); the cassette/acoustic side is the Q-bit FSK path (TIN/TOUT opcodes 0x0D/0x3B, EF2/EF3 handshake).
- The ICL8211CPA is the low-battery detector feeding INP 1 bit 3.
- The MM74C154/MM74C42 decoders define the RAM decode - confirming the RAM window (0x8000-0x8FFF in the current XML) still needs the schematic.
- No interrupt controller exists on any board - consistent with the firmware being purely polled.