I/O Map
The MSI/88e uses polled OUT/INP instructions for all peripheral I/O: the display, the keyboard, the mode switch, and the cassette recorder / acoustic interface. There is no interrupt mechanism and no DMA; the firmware polls all devices in its main loop (see also the Keyboard section for the multiplexed keyboard scan and the Display section for the display refresh).
Output Ports
OUT 1 |
Display segment LOW byte (segments A-F plus the middle bar). Written with 0x00 before each digit select as an anti-ghost blank, and output once at reset (OUT 1, IDL). |
OUT 2 |
Display digit select: 0x43 selects digit 0 (frame start), 0x42 selects the next digit. The digit-select lines double as keyboard row strobes. Additional strobe values (0x40, 0x02, 0x00) are used for mode/load control. |
OUT 3 |
Display segment / digit select, referenced only from a data-table region of the disassembly. Not used by the display refresh. |
OUT 4 |
Display segment HIGH byte (diagonal and centre segments, bits 8-13). |
OUT 5 |
Serial/Q-bit context-restore strobe (used at 0x175D and 0x179E in the Q-bit serial code). Not a keyboard strobe. |
OUT 6 |
Recorder/tape motor and handshake control. The SEND function writes a control byte here and then polls INP 6 until the recorder is ready. |
OUT 7 |
Recorder data / timing (SEND data byte). |
Input Ports
INP 0 |
Parallel/byte read (single occurrence, N=0). |
INP 1 |
Keyboard columns: bits 0-2 and bit 6, active low (all 1s = no key). The remaining bits are status inputs: bit 3 = battery/voltage flag, bit 4 = key/status line polled by the boot code. |
INP 2 |
Mode switches (low bits 0-1), including the OPER/PRGM slide switch. |
INP 3 |
Miscellaneous status (two occurrences). |
INP 4 |
Data-table byte (single occurrence at 0x11E0, inside a data region of the disassembly). Not a keyboard read. |
INP 5 |
Data-table byte (single occurrence at 0x1255, inside a data region of the disassembly). Not a keyboard read. |
INP 6 |
Recorder busy/ready status. The firmware polls this port (INP 6, shift, branch) until the recorder signals ready. |
INP 7 |
Data-table byte (single occurrence at 0x124F, inside a data region of the disassembly). Not a keyboard read. |
EF Flags and Q Line
Q |
Cassette/acoustic FSK transmit data. The firmware bit-bangs serial output on Q (SEQ/REQ with timing loops around 0x0D6C-0x0DC0) for the cassette recorder and the acoustic coupler. |
EF1 |
Status flag. |
EF2 |
Status flag / serial handshake. |
EF3 |
Tape/recorder/clock flag (heavily used). |
EF4 |
Tape/recorder/clock flag (heavily used, tested together with EF3). |
Interrupts
The firmware does not use the CDP1802 interrupt mechanism at all; there is no interrupt handler in the ROM. Register R1 is a working register used for computed jumps, not a reserved interrupt vector. A boot trace (1.7 million instructions) shows zero interrupts and zero DMA operations. The DIS followed by IDL at the end of boot is the terminal powering down to save the batteries when no program is loaded. This is not an interrupt-driven wait.