The Victory MPT-02 uses the CDP 1864 for video output. For details on the CDP 1861 please see the data sheets for this chip or the 'summary' on the CDP 1861 page. The Victory MPT-02 controls the CDP 1864 via INP 1 to switch the display on and EF1 to indicate the display status. OUT 1 is used to step the background colour (not sure which background colours are used).
The Victory MPT-02 firmware uses the resolution of 64 x 32 with interrupt routine entry point at @001C and display memory at @0900-@09FF.
The colour RAM can be written by writing to address location @0B00-@0B3F. The Victory probably has a 64 x 4 bit colour RAM. Every 8 x 4 set of pixels will have the same colour which results in a use of max 64 x 4 bits. To achieve this I expect address bit 3 and 4 are not used and bit 5 to 8 are shifted 2 bit to the right. Colour RAM is also aligned with the display memory. So location @0900 in display memory defines the first 8 pixels of the screen and colour RAM location #00 (address bit 3 and 4 removed) defines the colour for these 8 pixels. The same #00 colour RAM location also defines the colour for display memory location @0908, i.e. the first 8 pixels on row 2, @0910 and @0918. In total 8 Colours are supported.
The display status is an active low output signal occurring for a period of four horizontal cycles prior to the beginning and end of the 196 line display window. The signal is used by the firmware interrupt routine to indicate the last 'row' of the display area.