The ETI 660 uses the CDP 1864 for video output. For details on the CDP 1861 please see the data sheets for this chip or the 'summary' on the CDP 1861 page. The ETI 660 controls the CDP 1864 via INP 4 to switch the display off, INP 1 to switch the display on and EF1 to indicate the display status. OUT 1 is used to step the background colour, from blue to black to green to red and then back to blue.
The ETI 660 firmware uses the CDP 1864 with a resolution of 64 x 48 with interrupt routine entry point at @0138 and display memory at @0480-@0600.
The colour RAM can be written using OUT 3, both address and data values are used. The ETI 660 has a 256 x 4 bit colour RAM. Every 8 x 2 set of pixels will have the same colour which results in a use of 192 x 4 bits. To achieve this address bit 3 is not used and bit 4 to 8 are shifted 1 bit to the right. Colour RAM is also aligned with the display memory. So location @0480 in display memory defines the first 8 pixels of the screen and colour RAM location #40 (address bit 3 removed) defines the colour for these 8 pixels. The same #40 colour RAM location also defines the colour for display memory location @0488, i.e. the first 8 pixels on row 2.
The following 8 Colours are supported:
Note that the ETI 660 will start up in black & white mode (or actually blue and white). Colour use is initiated via the PIA MC6821 by selecting the Data Direction Register (OUT 2 with data bit 2 = 1 and address bit 0 = 1, bit 1 = 0.
The display status is an active low output signal occurring for a period of four horizontal cycles prior to the beginning and end of the 196 line display window. The signal is used by the firmware interrupt routine to indicate the last 'row' of the display area.