This is the only 'CPU' in Emma 02 which is not a CPU from the 180x series. Instead it is using a chip set as was used in the RCA SYSTEM00 prototype. The SYSTEM00 chip set is likely constructed largely of 7400-series TTL logic, i.e. not a microprocessor. For more details on the SYSTEM00 see also Herb Johnson's page System 00 inspection. The instruction set uses a subset of the 1801 with some incompatible differences and is likely what the 1801 was based on. An overview of all difference between the SYSTEM00, CDP1801 and CDP1802 can be found on the differences page.
This info is also available online on the Emma 02 site.
| xx | 8 bit value |
| RN | Register number N (N = 0 to F), RN can also be represented as N in all commands |
| RX | Stack or data pointer register |
| RP | Program counter register |
| RN.0, RX.0 or RP.0 | Lower order byte or RN, RX or RP |
| RN.00 | Lower order nibble or RN.0 |
| RN.1, RX.1 or RP.1 | Higher order byte or RN, RX or RP |
| D0 | Lower order nibble or D |
| M(RN)->D; RN+1->RN | This notation means: The memory byte pointed to by RN is loaded into D, and RN is incremented by 1. |
| INSTRUCTION | MNEMONIC | OP CODE | OPERATION |
| MEMORY REFERENCE | |||
| LOAD ADVANCE | LDA RN | 4N | M(RN)->D; RN+1->RN |
| LOAD VIA X | LDX | F0 | M(RX)->D |
| STORE VIA N | STR | 5N | D->M(RN) |
| REGISTER OPERATIONS | |||
| INCREMENT REG N | INC RN | 1N | RN+1->RN |
| DECREMENT REG N | DEC RN | 2N | RN-1->RN |
| GET LOW REG N | GLO RN | 8N | RN.0->D |
| PUT LOW REG N | PLO RN | AN | D->RN.0 |
| GET HIGH REG N | GHI RN | 9N | RN.1->D |
| PUT HIGH REG N | PHI RN | BN | D->RN.1 |
| PUT NIBBLE REG N | PNI RN | CN | D0->RN.00 |
| LOGIC OPERATIONS | |||
| OR | OR | F1 | M(RX) OR D->D |
| EXCLUSIVE OR | XOR | F3 | M(RX) XOR D->D |
| AND | AND | F2 | M(RX) AND D->D |
| SHIFT RIGHT | SHR | F6 | SHIFT D RIGHT, LSB(D)->DF, 0->MSB(D) |
| ARITHMETIC OPERATIONS | |||
| ADD | ADD | F4 | M(RX)+D->DF, D |
| SUBtrACT D | SD | F5 | M(RX)-D->DF, D |
| BRANCH INSTRUCTIONS-SHORT BRANCH | |||
| SHORT BRANCH | BR xx | 30 | M(RP)->RP.0 |
| SHORT BRANCH IF D NOT 0 | BNZ xx | 31 | IF D NOT 0, M(RP)->RP.0, ELSE RP+1->RP |
| SHORT BRANCH IF D=0 | BZ xx | 32 | IF D=0, M(RP)->RP.0, ELSE RP+1->RP |
| SHORT BRANCH IF DF=1 | BDF xx | 33 | IF DF=1, M(RP)->RP.0, ELSE RP+1->RP |
| SHORT BRANCH IF POS OR ZERO | BPZ xx | 33 | IF DF=1, M(RP)->RP.0, ELSE RP+1->RP |
| SHORT BRANCH IF GREATER OR EQUAL | BGE xx | 33 | IF DF=1, M(RP)->RP.0, ELSE RP+1->RP |
| SHORT BRANCH IF EF1=1 | B1 xx | 34 | IF EF1=1, M(RP)->RP.0, ELSE RP+1->RP |
| SHORT BRANCH IF EF2=1 | B2 xx | 35 | IF EF2=1, M(RP)->RP.0, ELSE RP+1->RP |
| SHORT BRANCH IF EF3=1 | B3 xx | 36 | IF EF3=1, M(RP)->RP.0, ELSE RP+1->RP |
| SHORT BRANCH IF EF4=1 | B4 xx | 37 | IF EF4=1, M(RP)->RP.0, ELSE RP+1->RP |
| CONTROL INSTRUCTIONS | |||
| IDLE RN | IDL RN | 0N | WAIT FOR DMA OR INTERRUPT; M(RN)->LEDs |
| SET P | SEP RN | DN | N->P |
| SET X | SEX RN | EN | N->X |
| SAVE | SAV | 78 | T->M(RX) |
| RETURN | RET | 70 | M(RX)->(X, P); RX+1->RX, 1->lE |
| INPUT-OUTPUT BYTE TRANSFER | |||
| OUTPUT 1 | OUT 1 | 61 | M(RX)->BUS; RX+1->RX; N LINES=1 |
| OUTPUT 2 | OUT 2 | 62 | M(RX)->BUS; RX+1->RX; N LINES=2, |
| OUTPUT 3 | OUT 3 | 63 | M(RX)->BUS; RX+1->RX; N LINES=3 |
| INPUT 0 | INP 0 | 68 | BUS->M(RX); BUS->D; N LINES=1 |