I believe the most used 180x CPU is the CDP1802, below is the complete instruction set. The 1802 was introduced by RCA in 1976, successors of the 1802 are the CDP1804, CDP1805 and CDP1806 with extended instruction sets which you can find on the linked pages. An overview of all difference between the SYSTEM00, CDP1801 and CDP1802 can be found on the differences page.
This info is also available online on the Emma 02 site.
| xx | 8 bit value |
| xxxx | 16 bit value |
| RN | Register number N (N = 0 to F), RN can also be represented as N in all commands |
| RX | Stack or data pointer register |
| RP | Program counter register |
| RN.0, RX.0 or RP.0 | Lower order byte or RN, RX or RP |
| RN.1, RX.1 or RP.1 | Higher order byte or RN, RX or RP |
| M(RN)->D; RN+1->RN | This notation means: The memory byte pointed to by RN is loaded into D, and RN is incremented by 1. |
| INSTRUCTION | MNEMONIC | OP CODE | OPERATION |
| MEMORY REFERENCE | |||
| LOAD VIA N | LDN RN | 0N | M(RN)->D; FOR N not 0 |
| LOAD ADVANCE | LDA RN | 4N | M(RN)->D; RN+1->RN |
| LOAD VIA X | LDX | F0 | M(RX)->D |
| LOAD VIA X AND ADVANCE | LDXA | 72 | M(RX)->D; RX+1->RX |
| LOAD IMMEDIATE | LDI xx | F8 | M(RP)->D; RP+1->RP |
| STORE VIA N | STR | 5N | D->M(RN) |
| STORE VIA X AND DECREMENT | STXD | 73 | D->M(RX); RX-1->RX |
| REGISTER OPERATIONS | |||
| INCREMENT REG N | INC RN | 1N | RN+1->RN |
| DECREMENT REG N | DEC RN | 2N | RN-1->RN |
| INCREMENT REG X | IRX | 60 | RX+1->RX |
| GET LOW REG N | GLO RN | 8N | RN.0->D |
| PUT LOW REG N | PLO RN | AN | D->RN.0 |
| GET HIGH REG N | GHI RN | 9N | RN.1->D |
| PUT HIGH REG N | PHI RN | BN | D->RN.1 |
| LOGIC OPERATIONS | |||
| OR | OR | F1 | M(RX) OR D->D |
| OR IMMEDIATE | ORI xx | F9 | M(RP) OR D->D; RP+1->RP |
| EXCLUSIVE OR | XOR | F3 | M(RX) XOR D->D |
| EXCLUSIVE OR IMMEDIATE | XRI xx | FB | M(RP) XOR D->D; RP+1->RP |
| AND | AND | F2 | M(RX) AND D->D |
| AND IMMEDIATE | ANI xx | FA | M(RP) AND D->D; RP+1->RP |
| SHIFT RIGHT | SHR | F6 | SHIFT D RIGHT, LSB(D)->DF, 0->MSB(D) |
| SHIFT RIGHT WITH CARRY | SHRC | 76 | SHIFT D RIGHT, LSB(D)->DF, DF->MSB(D) |
| RING SHIFT RIGHT | RSHR | 76 | SHIFT D RIGHT, LSB(D)->DF, DF->MSB(D) |
| SHIFT LEFT | SHL | FE | SHIFT D LEFT, MSB(D)->DF, 0->LSB(D) |
| SHIFT LEFT WITH CARRY | SHLC | 7E | SHIFT D LEFT, MSB(D)->DF, DF->LSB(D) |
| RING SHIFT LEFT | RSHL | 7E | SHIFT D LEFT, MSB(D)->DF, DF->LSB(D) |
| ARITHMETIC OPERATIONS | |||
| ADD | ADD | F4 | M(RX)+D->DF, D |
| ADD IMMEDIATE | ADI xx | FC | M(RP)+D->DF, D; RP+1->RP |
| ADD WITH CARRY | ADC | 74 | M(RX)+D+DF->DF, D |
| ADD WITH CARRY, IMMEDIATE | ADCI xx | 7C | M(RP)+D+DF->DF, D; RP+1->RP |
| SUBTRACT D | SD | F5 | M(RX)-D->DF, D |
| SUBTRACT D IMMEDIATE | SDI xx | FD | M(RP)-D->DF, D; RP+1->RP |
| SUBTRACT D WITH BORROW | SDB | 75 | M(RX)-D-(NOT DF)->DF, D |
| SUBTRACT D WITH BORROW, IMMEDIATE | SDBI xx | 7D | M(RP)-D-(Not DF)->DF, D; RP+1->RP |
| SUBTRACT MEMORY | SM | F7 | D-M(RX)->DF, D |
| SUBTRACT MEMORY IMMEDIATE | SMI xx | FF | D-M(RP)->DF, D; RP+1->RP |
| SUBTRACT MEMORY WITH BORROW | SMB | 77 | D-M(RX)-(NOT DF)->DF, D |
| SUBTRACT MEMORY WITH BORROW, IMMEDI¬ATE | SMBl xx | 7F | D-M(RP)-(NOT DF)->DF, D; RP+1->RP |
| BRANCH INSTRUCTIONS-SHORT BRANCH | |||
| SHORT BRANCH | BR xx | 30 | M(RP)->RP.0 |
| NO SHORT BRANCH (See SKP) | NBR | 38 | RP+1->RP |
| SHORT BRANCH IF D=0 | BZ xx | 32 | IF D=0, M(RP)->RP.0, ELSE RP+1->RP |
| SHORT BRANCH IF D NOT 0 | BNZ xx | 3A | IF D NOT 0, M(RP)->RP.0, ELSE RP+1->RP |
| SHORT BRANCH IF DF=1 | BDF xx | 33 | IF DF=1, M(RP)->RP.0, ELSE RP+1->RP |
| SHORT BRANCH IF POS OR ZERO | BPZ xx | 33 | IF DF=1, M(RP)->RP.0, ELSE RP+1->RP |
| SHORT BRANCH IF GREATER OR EQUAL | BGE xx | 33 | IF DF=1, M(RP)->RP.0, ELSE RP+1->RP |
| SHORT BRANCH IF DF=0 | BNF xx | 3B | IF DF=0, M(RP)->RP.0, ELSE RP+1->RP |
| SHORT BRANCH IF MINUS | BM xx | 3B | IF DF=0, M(RP)->RP.0, ELSE RP+1->RP |
| SHORT BRANCH IF LESS | BL xx | 3B | IF DF=0, M(RP)->RP.0, ELSE RP+1->RP |
| SHORT BRANCH IF Q=1 | BQ xx | 31 | IF Q=1, M(RP)->RP.0, ELSE RP+1->RP |
| SHORT BRANCH IF Q=0 | BNQ xx | 39 | IF Q=0, M(RP)->RP.0, ELSE RP+1->RP |
| SHORT BRANCH IF EF1=1 | B1 xx | 34 | IF EF1=1, M(RP)->RP.0, ELSE RP+1->RP |
| SHORT BRANCH IF EF1=0 | BN1 xx | 3C | IF EF1=0, M(RP)->RP.0, ELSE RP+1->RP |
| SHORT BRANCH IF EF2=1 | B2 xx | 35 | IF EF2=1, M(RP)->RP.0, ELSE RP+1->RP |
| SHORT BRANCH IF EF2=0 | BN2 xx | 3D | IF EF2=0, M(RP)->RP.0, ELSE RP+1->RP |
| SHORT BRANCH IF EF3=1 | B3 xx | 36 | IF EF3=1, M(RP)->RP.0, ELSE RP+1->RP |
| SHORT BRANCH IF EF3=0 | BN3 xx | 3E | IF EF3=0, M(RP)->RP.0, ELSE RP+1->RP |
| SHORT BRANCH IF EF4=1 | B4 xx | 37 | IF EF4=1, M(RP)->RP.0, ELSE RP+1->RP |
| SHORT BRANCH IF EF4=0 | BN4 xx | 3F | IF EF4=0, M(RP)->RP.0, ELSE RP+1->RP |
| BRANCH INSTRUCTIONS-LONG BRANCH | |||
| LONG BRANCH | LBR xxxx | C0 | M(RP)->RP. 1, M(RP+1)->RP.0 |
| NO LONG BRANCH (See LSKP) | NLBR | C8 | RP+2->RP |
| LONG BRANCH IF D=0 | LBZ xxxx | C2 | lF D=0, M(RP)->RP.1, M(RP+1)->RP.0, ELSE RP+2->RP |
| LONG BRANCH IF D NOT 0 | LBNZ xxxx | CA | IF D Not 0, M(RP)->RP.1, M(RP+1)->RP.0, ELSE RP+2->RP |
| LONG BRANCH IF DF=1 | LBDF xxxx | C3 | IF DF=1, M(RP)->RP.1, M(RP+1)->RP.0, ELSE RP+2->RP |
| LONG BRANCH IF DF=0 | LBNF xxxx | CB | IF DF=0, M(RP)->RP.1, M(RP+1)->RP.0, ELSE RP+2->RP |
| LONG BRANCH IF Q=1 | LBQ xxxx | C1 | IF Q=1, M(RP)->RP.1, M(RP+1)->RP.0, ELSE RP+2->RP |
| LONG BRANCH lF Q=0 | LBNQ xxxx | C9 | lF Q=0, M(RP)->RP.1, M(RP+1)->RP.0 ELSE RP+2->RP |
| SKIP INSTRUCTIONS | |||
| SHORT SKIP (See NBR) | SKP | 38 | RP+1->RP |
| LONG SKIP (See NLBR) | LSKP | C8 | RP+2->RP |
| LONG SKIP IF D=0 | LSZ | CE | IF D=0, RP+2->RP, ELSE CONTINUE |
| LONG SKIP IF D NOT 0 | LSNZ | C6 | IF D Not 0, RP+2->RP, ELSE CONTINUE |
| LONG SKIP IF DF=1 | LSDF | CF | IF DF=1, RP+2->RP, ELSE CONTINUE |
| LONG SKIP IF DF=0 | LSNF | C7 | IF DF=0, RP+2->RP, ELSE CONTINUE |
| LONG SKIP lF Q=1 | LSQ | CD | IF Q=1, RP+2->RP, ELSE CONTINUE |
| LONG SKIP IF Q=0 | LSNQ | C5 | IF Q=0, RP+2->RP, ELSE CONTINUE |
| LONG SKIP IF IE=1 | LSIE | CC | IF IE=1, RP+2->RP, ELSE CONTINUE |
| CONTROL INSTRUCTIONS | |||
| IDLE | IDL | 00 | WAIT FOR DMA OR INTERRUPT; M(R0)->BUS |
| NO OPERATION | NOP | C4 | CONTINUE |
| SET P | SEP RN | DN | N->P |
| SET X | SEX RN | EN | N->X |
| SET Q | SEQ | 7B | 1->Q |
| RESET Q | REQ | 7A | 0->Q |
| SAVE | SAV | 78 | T->M(RX) |
| PUSH X, P TO STACK | MARK | 79 | (X, P)->T; (X, P)->M(R2), THEN P->X; R2-1->R2 |
| RETURN | RET | 70 | M(RX)->(X, P); RX+1->RX, 1->lE |
| DISABLE | DlS | 71 | M(RX)->(X, P); RX+1->RX, 0->lE |
| INPUT-OUTPUT BYTE TRANSFER | |||
| OUTPUT 1 | OUT 1 | 61 | M(RX)->BUS; RX+1->RX; N LINES=1 |
| OUTPUT 2 | OUT 2 | 62 | M(RX)->BUS; RX+1->RX; N LINES=2 |
| OUTPUT 3 | OUT 3 | 63 | M(RX)->BUS; RX+1->RX; N LINES=3 |
| OUTPUT 4 | OUT 4 | 64 | M(RX)->BUS; RX+1->RX; N LINES=4 |
| OUTPUT 5 | OUT 5 | 65 | M(RX)->BUS; RX+1->RX; N LINES=5 |
| OUTPUT 6 | OUT 6 | 66 | M(RX)->BUS; RX+1->RX; N LINES=6 |
| OUTPUT 7 | OUT 7 | 67 | M(RX)->BUS; RX+1->RX; N LINES=7 |
| INPUT 1 | INP 1 | 69 | BUS->M(RX); BUS->D; N LINES=1 |
| INPUT 2 | INP 2 | 6A | BUS->M(RX); BUS->D; N LINES=2 |
| INPUT 3 | INP 3 | 6B | BUS->M(RX); BUS->D; N LINES=3 |
| INPUT 4 | INP 4 | 6C | BUS->M(RX); BUS->D; N LINES=4 |
| INPUT 5 | INP 5 | 6D | BUS->M(RX); BUS->D; N LINES=5 |
| INPUT 6 | INP 6 | 6E | BUS->M(RX); BUS->D; N LINES=6 |
| INPUT 7 | INP 7 | 6F | BUS->M(RX); BUS->D; N LINES=7 |