The CDP1801 was the first microprocessor developed by RCA it is a 2-chip implementation which became the 1802. An overview of all difference between the SYSTEM00, CDP1801 and CDP1802 can be found on the differences page.
This info is also available online on the Emma 02 site.
| xx | 8 bit value |
| RN | Register number N (N = 0 to F), RN can also be represented as N in all commands |
| RX | Stack or data pointer register |
| RP | Program counter register |
| RN.0, RX.0 or RP.0 | Lower order byte or RN, RX or RP |
| RN.1, RX.1 or RP.1 | Higher order byte or RN, RX or RP |
| M(RN)->D; RN+1->RN | This notation means: The memory byte pointed to by RN is loaded into D, and RN is incremented by 1. |
| INSTRUCTION | MNEMONIC | OP CODE | OPERATION |
| MEMORY REFERENCE | |||
| LOAD ADVANCE | LDA RN | 4N | M(RN)->D; RN+1->RN |
| LOAD VIA X | LDX | F0 | M(RX)->D |
| LOAD IMMEDIATE | LDI xx | F8 | M(RP)->D; RP+1->RP |
| STORE VIA N | Str | 5N | D->M(RN) |
| REGISTER OPERATIONS | |||
| INCREMENT REG N | INC RN | 1N | RN+1->RN |
| DECREMENT REG N | DEC RN | 2N | RN-1->RN |
| GET LOW REG N | GLO RN | 8N | RN.0->D |
| PUT LOW REG N | PLO RN | AN | D->RN.0 |
| GET HIGH REG N | GHI RN | 9N | RN.1->D |
| PUT HIGH REG N | PHI RN | BN | D->RN.1 |
| LOGIC OPERATIONS | |||
| OR | OR | F1 | M(RX) OR D->D |
| OR IMMEDIATE | ORI xx | F9 | M(RP) OR D->D; RP+1->RP |
| EXCLUSIVE OR | XOR | F3 | M(RX) XOR D->D |
| EXCLUSIVE OR IMMEDIATE | XRI xx | FB | M(RP) XOR D->D; RP+1->RP |
| AND | AND | F2 | M(RX) AND D->D |
| AND IMMEDIATE | ANI xx | FA | M(RP) AND D->D; RP+1->RP |
| SHIFT RIGHT | SHR | F6 | SHIFT D RIGHT, LSB(D)->DF, 0->MSB(D) |
| SHIFT LEFT | SHL | FE | SHIFT D LEFT, MSB(D)->DF, 0->LSB(D) |
| ARITHMETIC OPERATIONS | |||
| ADD | ADD | F4 | M(RX)+D->DF, D |
| ADD IMMEDIATE | ADI xx | FC | M(RP)+D->DF, D; RP+1->RP |
| SUBtrACT D | SD | F5 | M(RX)-D->DF, D |
| SUBtrACT D IMMEDIATE | SDI xx | FD | M(RP)-D->DF, D; RP+1->RP |
| SUBtrACT MEMORY | SM | F7 | D-M(RX)->DF, D |
| SUBtrACT MEMORY IMMEDIATE | SMI xx | FF | D-M(RP)->DF, D; RP+1->RP |
| BRANCH INSTRUCTIONS-SHORT BRANCH | |||
| SHORT BRANCH | BR xx | 30 | M(RP)->RP.0 |
| NO SHORT BRANCH (See SKP) | NBR | 38 | RP+1->RP |
| SHORT BRANCH IF D=0 | BZ xx | 32 | IF D=0, M(RP)->RP.0, ELSE RP+1->RP |
| SHORT BRANCH IF D NOT 0 | BNZ xx | 3A | IF D NOT 0, M(RP)->RP.0, ELSE RP+1->RP |
| SHORT BRANCH IF DF=1 | BDF xx | 33 | IF DF=1, M(RP)->RP.0, ELSE RP+1->RP |
| SHORT BRANCH IF POS OR ZERO | BPZ xx | 33 | IF DF=1, M(RP)->RP.0, ELSE RP+1->RP |
| SHORT BRANCH IF GREATER OR EQUAL | BGE xx | 33 | IF DF=1, M(RP)->RP.0, ELSE RP+1->RP |
| SHORT BRANCH IF DF=0 | BNF xx | 3B | IF DF=0, M(RP)->RP.0, ELSE RP+1->RP |
| SHORT BRANCH IF MINUS | BM xx | 3B | IF DF=0, M(RP)->RP.0, ELSE RP+1->RP |
| SHORT BRANCH IF LESS | BL xx | 3B | IF DF=0, M(RP)->RP.0, ELSE RP+1->RP |
| SHORT BRANCH IF EF1=1 | B1 xx | 34 | IF EF1=1, M(RP)->RP.0, ELSE RP+1->RP |
| SHORT BRANCH IF EF1=0 | BN1 xx | 3C | IF EF1=0, M(RP)->RP.0, ELSE RP+1->RP |
| SHORT BRANCH IF EF2=1 | B2 xx | 35 | IF EF2=1, M(RP)->RP.0, ELSE RP+1->RP |
| SHORT BRANCH IF EF2=0 | BN2 xx | 3D | IF EF2=0, M(RP)->RP.0, ELSE RP+1->RP |
| SHORT BRANCH IF EF3=1 | B3 xx | 36 | IF EF3=1, M(RP)->RP.0, ELSE RP+1->RP |
| SHORT BRANCH IF EF3=0 | BN3 xx | 3E | IF EF3=0, M(RP)->RP.0, ELSE RP+1->RP |
| SHORT BRANCH IF EF4=1 | B4 xx | 37 | IF EF4=1, M(RP)->RP.0, ELSE RP+1->RP |
| SHORT BRANCH IF EF4=0 | BN4 xx | 3F | IF EF4=0, M(RP)->RP.0, ELSE RP+1->RP |
| SKIP INStrUCTIONS | |||
| SHORT SKIP (See NBR) | SKP | 38 | RP+1->RP |
| CONtrOL INStrUCTIONS | |||
| IDLE | IDL | 00 | WAIT FOR DMA OR INTERRUPT; M(R0)->BUS |
| SET P | SEP RN | DN | N->P |
| SET X | SEX RN | EN | N->X |
| SAVE | SAV | 78 | T->M(RX) |
| RETURN | RET | 70 | M(RX)->(X, P); RX+1->RX, 1->lE |
| DISABLE | DlS | 71 | M(RX)->(X, P); RX+1->RX, 0->lE |
| INPUT-OUTPUT BYTE trANSFER | |||
| OUTPUT 0 | OUT 0 | 60 | M(RX)->BUS; RX+1->RX; N LINES=1, this is not formally documented but should work as an OUT 0 |
| OUTPUT 1 | OUT 1 | 61 | M(RX)->BUS; RX+1->RX; N LINES=1 |
| OUTPUT 2 | OUT 2 | 62 | M(RX)->BUS; RX+1->RX; N LINES=2 |
| OUTPUT 3 | OUT 3 | 63 | M(RX)->BUS; RX+1->RX; N LINES=3 |
| OUTPUT 4 | OUT 4 | 64 | M(RX)->BUS; RX+1->RX; N LINES=4 |
| OUTPUT 5 | OUT 5 | 65 | M(RX)->BUS; RX+1->RX; N LINES=5 |
| OUTPUT 6 | OUT 6 | 66 | M(RX)->BUS; RX+1->RX; N LINES=6 |
| OUTPUT 7 | OUT 7 | 67 | M(RX)->BUS; RX+1->RX; N LINES=7 |
| INPUT 0 | INP 0 | 68 | BUS->M(RX); BUS->D; N LINES=1, this is not formally documented but should work as an INP 0 |
| INPUT 1 | INP 1 | 69 | BUS->M(RX); BUS->D; N LINES=1 |
| INPUT 2 | INP 2 | 6A | BUS->M(RX); BUS->D; N LINES=2 |
| INPUT 3 | INP 3 | 6B | BUS->M(RX); BUS->D; N LINES=3 |
| INPUT 4 | INP 4 | 6C | BUS->M(RX); BUS->D; N LINES=4 |
| INPUT 5 | INP 5 | 6D | BUS->M(RX); BUS->D; N LINES=5 |
| INPUT 6 | INP 6 | 6E | BUS->M(RX); BUS->D; N LINES=6 |
| INPUT 7 | INP 7 | 6F | BUS->M(RX); BUS->D; N LINES=7 |